1. Field of Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to an optimized control circuit for generating a full signal in a First In First Out (FIFO) device.
2. Related Art
Data transfer in computer systems is typically conducted between a sending element and a receiving element according to a handshake protocol. In computer systems, data is often transmitted from the sending element at a higher rate than it can be consumed at the receiving element. In order to facilitate data communication between the sending element and the receiving element, high-speed buffers such as First In First Out (FIFO) memory devices are used.
A FIFO device typically comprises a plurality of serially arranged storage cells (or memory locations) which are sequentially written into and read from. A write address pointer holds the write binary address of the storage cell into which data will be written during the next write operation, and a read address pointer holds the read binary address of the storage cell from which data will be read during the next read operation.
FIG. 1 illustrates a conventional FIFO device 100. FIFO device 100 comprises: a FIFO memory element 101, a write address circuit 103, a write multiplexer 105, a read address circuit 107, a read multiplexer 109, an up-down counter 111, and a FULL/EMPTY signal generator 113. Moreover, memory element 101 may be a RAM (Random Access Memory) in which reading and writing of data may be performed simultaneously and comprises a capacity of N words. While a read permission signal (RE) is asserted, data (RDATA) is read from an address designated by a read address (RADR) on a word-by-word basis at a clock timing of a clock signal CLK. Similarly, while a write permission signal (WE) is asserted, data (WDATA) is written into an address designated by a write address (WADR) on a word-by-word basis at a clock timing of the clock signal CLK.
The read address circuit 107 receives the clock signal CLK and the read permission signal (RE). While the read permission signal (RE) is asserted, the read address circuit 107 increments the read address (RADR) by one at a clock timing of the clock signal CLK.
The write address circuit 103 receives the clock signal CLK and the write permission (WE). While the write permission signal (WE) is asserted, the write address circuit 103 increments the write address (WADR) by one at a clock timing of the write clock signal CLK.
When up-down counter 111 receives an asserted write enable (WE) signal, the counter enables a count-up signal (U) which allows a count-up operation. Moreover, when up-down counter 111 receives an asserted read enable (RE) signal, the counter enables a count-down signal (D) which allows a count-down operation. While one of the count-up enable signal (U) or the count-down enable signal (D) is asserted, the up-down counter 111 performs a count operation at a clock timing of the clock CLK. A count value count of the up-down counter 111 is output to FULL/EMPTY signal generator 113.
Signal generator 113 receives the count value count from up-down counter 111. If the received count value count is 0, the signal generator 113 outputs an empty signal E, indicating that memory 101 has no data to be read.
In one embodiment of a conventional FIFO device, pipelines are not used in conjunction with the FIFO device. In this embodiment, if the received count value count equals N (the number of words available in memory 101), signal generator 113 outputs a full signal F, indicating that memory 101 has no more storage capacity available.
In an alternate embodiment of a conventional FIFO device, pipelines are used in conjunction with the FIFO device. In this alternate embodiment, assuming M number of pipelines are used wherein each pipeline is capable of storing one data word, if the received count value count equals N (the number of words available in memory 101)—M (the maximum number of words stored in the pipelines), signal generator 113 outputs a full signal F, indicating that memory 101 has no more storage capacity available. As an illustrative example, FIFO memory 101 in FIG. 1 receives data from 5 pipelines denoted Pipeline0, Pipeline1, Pipeline2, Pipeline3, and Pipeline4. In this example, signal generator 113 generates a full signal F if count equals to N−5.
The conventional FIFO device illustrated in FIG. 1 may be used to facilitate the data rate discrepancy between the sending element and the receiving element. However, such conventional FIFO devices do not take into consideration possible idle pipelines that do not contain any data, and therefore may generate a full signal while the FIFO memory is still capable of storing additional data.